- tRFC, tFAW, tRRD, tRRDL and tSTAG control internal DRAM processes and primarily affect stability.
- Many subtimings are interrelated; forcing them too much can reduce performance or cause errors.
- XMP profiles typically offer a very solid balance between security and speed for real-world use.
- Adjusting subtimings only provides marginal improvements compared to optimizing frequency, main timings, and voltage.
When you start tinkering with RAM, the first thing you look at are the main timings: CL, tRCD, tRP and TRASBut as soon as you delve a little deeper, acronyms like appear. tRFC, tFAW, tRRD, tRRDL and tSTAG that sound like gibberish and are almost never explained well. Many users see these values change when update the modules or activate an XMP profile and wonder if they really matter in day-to-day life, especially for gaming or productivity tasks.
The reality is that these timings are internal parameters that govern how memory physically worksThese settings don't always translate into higher FPS or benchmark scores, but they do make the difference between a stable system and one that crashes at the slightest lapse in attention. Furthermore, incorrectly tuning them can have the opposite effect: reduced performance despite having "more aggressive" values. Let's see why this happens and what each timing setting looks like.
What are tRFC, tFAW, tRRD, tRRDL, and tSTAG in RAM?
In the RAM specifications, you'll see that, in addition to the four main timings, there's a long list of sub-timings. Among them are: tRFC, tFAW, tRRD, tRRDL and tSTAG, which control critical internal operations of the DRAM chipsThey do not directly manage latency between the CPU and memory, but rather refresh times, activation between banks, and certain security limitations to prevent chips from becoming overloaded.
Many module manufacturers, such as G.SKILL, Crucial, or Patriot, These subtimings are programmed into the XMP or DOCP profiles after many stability and performance tests.That's why sometimes, when you try to "improve" them manually (by drastically lowering values), the result is a strange mix of instability, errors in MemTest, or even performance losses in synthetic tests like AIDA64 or membench.
It must be clear that, As long as the main timings are correct, these subtimings fine-tune details of how the work is distributed between memory banks and rows.Adjusting them might make a difference of thousandths or small percentages in benchmarks, but the absolute priority is that the system is stable under all loads: gaming, editing, prolonged tests, etc.
The role of tRFC: memory row refresh
The tRFC (Row Refresh Cycle Time) timing is one of the most important among the secondary timings. Control There minimum time the RAM must wait to complete a row refresh operationSince DRAM chips lose charge over time, they need to refresh their contents periodically to avoid data loss; tRFC determines how much a row is "locked" while that refresh is performed.
In some BIOS You will see several related fields: tRFC (in cycles), tRFC (ns), tRFC2 and tRFC4The value in nanoseconds is the real-time value, and the others are expressed in internal clock cycles. In a practical example of an ASUS ROG Strix G15 Advantage Edition, the stock RAM and a Crucial DDR4 3200 MHz CL22 RAM had exactly the same refresh rates:
- tRFC (ns) – 350
- tRFC – 560
- tRFC2 – 416
- tRFC4 – 256
Although the new RAM was double-sided and had better subtiming in other areas, The soft drink was priced at the same safe values.This is quite common: the manufacturer prioritizes long-term stability, especially in portable or equipment that will be switched on for many hours.
There is even a rule widely used in the overclocking community to relate these times: tRFC2 ≈ tRFC × 0,768 and tRFC4 ≈ tRFC × 0,46These are indicative proportions that help maintain consistency between the different refresh parameters when manually adjusting the base value.
To calculate an approximate tRFC in cycles from an estimated value in nanoseconds, many enthusiasts follow a simple formula: tRFC (cycles) ≈ (tRFC_ns × memory frequency) / number of channelsFor example, for 180 ns at 3600 MHz in dual channel0,18 × 3600 / 2 = 324 cycles. This type of calculation is useful for guidance, but it must then be validated with stability tests.
tFAW: activation limiter in time window
The tFAW (Four Activate Window) parameter is one of the most confusing. Define a time window in which only a maximum number of row activations can be performed within the same rank, usually four. It's a kind of "traffic light" that prevents the chip from overloading by opening too many rows at once.
A well-known rule in overclocking communities (and one that several users attribute to Korean guides from forums like OCN) states that tFAW should, as a general rule, be four times tRRDSIn other words, if tRRDS is 4, a tFAW of around 16 would be a very tight margin. In practice, commercial memory modules usually have a much higher tFAW (40, 44, 48…) to guarantee a safety margin.
It has been observed in several tests that, When tFAW drops below a certain point, performance starts to worsen instead of improve.A user who was fine-tuning his kit with XMP II found that:
- By reducing tFAW from 44 to 40, writing performance improved slightly (within the margin of error).
- As tFAW was further reduced below 40, read/write speeds and latency degraded.
Another case, with a Patriot Viper Steel kit at high frequency, showed an even clearer effect: Changing tFAW and tWR from 12 to 24 “for safety” caused performance in membench to plummet., although memory tests They didn't flag errors. When the user reverted to more aggressive values and properly adjusted other subtimings like tRFC, they obtained much better benchmarks without losing stability.
Practical conclusion: tFAW is not simply "the lower the better"It must be related to tRRDS and the internal design of the kit. Values that are too high or too low will ultimately limit performance, even if the memory passes basic error tests.
tRRD and tRRDL: minimum time between row activations
The timings tRRD (Row to Row Delay) and tRRDL (Row to Row Delay Long) mark the minimum interval between row activations in different banks. tRRDS usually refers to the short distance (Short) and tRRDL to the long distance (Long)which comes into play when activation affects banks further away within the chip.
In practice, these parameters limit how quickly the memory controller can jump between different rows to handle requests. If you set them too low, you may encounter instability or other safety mechanisms (such as tFAW) may kick in and slow down the rate..
In the example of the ASUS ROG Strix G15, when switching from the stock RAM to a dual-rank Crucial DDR4 3200 MHz CL22 kit, this difference occurred:
- Serial: tRRDS 9, tRRDL 11, tFAW 48, tSTAG 12.
- New RAM: tRRDS 4, tRRDL 8, tFAW 34, tSTAG 9.
Although the main timings remained the same, the subtiming was noticeably more aggressive on the RAM Crucial. Even so, In real-world use (gaming and productivity) the performance differences were minimal.The change was more noticeable in synthetic benchmarks than in everyday use.
Another user who was adjusting their XMP II profile encountered a curious situation with tRRDL: By lowering tRRDL from its initial value, the read, write, and latency results moved up and down within the margin of error.With tRRDL set to 8 or 9, the results were virtually equivalent to the base configuration; reducing it further caused performance to degrade. In other words, there's an optimal point beyond which further adjustments no longer help.
Many advanced guides recommend that tRRDL should not be forced too far below the values proposed by the XMP profile.This is especially true with dual-range (DR) modules, where electrical requirements are higher. The system's own behavior ends up "paying" for these excesses, sometimes with a decrease in performance that seems illogical on paper.
What is tSTAG and why is it hardly ever talked about?
tSTAG is one of those subtimings that usually appear in advanced BIOS and that almost nobody touches. It usually refers to a kind of "staggering" or stepped delay between certain commands internaldesigned to avoid signal conflicts when certain operations are chained together.
In the practical example of the ASUS laptop RAM, the switch from the stock memory to Crucial changed tSTAG from 12 to 9. It's a slightly more aggressive adjustment, but in practice it didn't produce a measurable jump in everyday benchmarks.This type of subtiming is adjusted more by internal requirements of the chip and controller than by a direct impact on performance.
That's why many experts in forums agree that When overclocking, the priority is to focus on the main timings and key sub-timings such as tRFC, tFAW, tRRD, tWTR, or tWR.Parameters such as tSTAG are usually left to the discretion of the BIOS auto or the values defined by the manufacturer.
Although you can experiment with them if you're looking to squeeze out the last 1% of performance, They're not the first place to look if you want a clear improvement for gaming or to speed up productivity tasks.The risk of causing rare instabilities without gaining anything appreciable usually outweighs the potential benefit.
Relationships and basic rules between timings
Anyone who has browsed overclocking forums will have seen tons of rules and formulas for relating timings. Some of the most frequently used are based on accumulated experiences of the community, such as those a user gathered from a well-known Korean “engineer” on OCN. These guidelines aren't set in stone, but they serve as a starting point.
There are also several common ways to calculate after:
- tRP + TRAS ≈ tRC
There are also several common ways to calculate TRAS:
- TRAS ≈ tRCD + tCL (the most used).
- TRAS ≈ tCL + tRP.
- tRAS ≈ tRCD + tWR + tBL (tBL is the Burst Length).
About tWR (Write Recovery Time)There are a number of "rules" to prevent it from being excessively low:
- tWR ≥ tRRDS + tWTRS
- tWR ≥ tCL + tRTP
- tWR ≥ TRAS − tRCD
If these minimum relationships are not respected, The system may pass some light tests but fail under heavier loads or after several hours of useIt's the typical case of "it seems stable, but the game crashes after a while".
Another interesting group of relationships affects tRDWR (Read to Write Delay)In some configurations, the following reference is used:
- tRDWR ≈ tRCD_RD / 2 as a base value.
From there, certain "safe" values are considered depending on whether the RAM is single-rank (SR) or dual-rank (DR):
- 2× SR: tRDWR = tRCD_RD / 2
- 4× SR: tRDWR = tRCD_RD / 2 + 1
- 2× DR: tRDWR = tRCD_RD + 2
- 4× DR: tRDWR = tRCD_RD + 4 (some people say that the value +3 may allow the use of a lower tWRRD).
These are all guidelines to avoid absurd combinations. You can deviate slightly from these rules to refine your approach, but the further you stray, the more likely you are to make subtle mistakes. that only appear after many hours of stress or in certain applications.
tWR, tWTR, tRTP and tCWL: subtimings that can be noticed
In addition to tRFC, tFAW, and tRRD, there are other very relevant subtimings in RAM behavior: tWR, tWTRS, tWTRL, tRTP and tCWLSeveral users have shared specific experiences where touching these values has clearly changed both stability and performance.
tWR (Write Recovery Time) marks the time the memory must wait after a write operation before it can execute certain subsequent operations. In the case of a user who followed the DRAM Calculator to relax tFAW and tWR from 12 to 24, the effect was striking: Memory became stable in tests like MemTest86, but times in membench took a brutal turn for the worse.In other words, it had gained stability, but at the cost of killing performance.
When that same user returned to more aggressive timings and simultaneously fine-tuned other parameters such as tRFC, tRFC2 and tRFC4, It achieved a configuration with CL15, tRCDRD 16 and very tight subtimings, stable in multiple passes of memtest and KarhuIt even slightly increased VDDP and VDDG to 0,9V and 0,95V to meet the recommended minimums, keeping the RAM voltage around 1,38V and the SoC at 1,1V.
Regarding tWTR (Write to Read), it is usually divided into tWTRS (Short) and tWTRL (Long). A widespread recommendation is that tWTRL is double or triple tRRDSThis allows sufficient time between writes and reads to avoid putting too much strain on the banks. Again, this is more of a practical guideline than a rigid rule, but it helps prevent problematic combinations.
tRTP (Read to Precharge) and tCWL (CAS Write Latency) also play a role. There is a fairly common pattern: tCWL is usually equal to tCLIf they don't match, the difference is often adjusted to a logical step, increasing or decreasing the value to maintain consistency. Lowering tCWL too much can cause instability without a measurable improvement outside of very specific benchmarks.
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